1. Field of the Invention
The present invention relates generally to memory devices and systems, and more particularly to, systems and method for sensing in memory devices.
2. Description of the Related Art
Contemporary volatile and non-volatile memory circuits have a large range of densities, are implemented using high density state of the art technologies for smallest die area, and require a fast read access time for the stored data. The read sensing circuits are also increasingly more affected by noise and process variations such that it is now critical for the sensing method to be robust as well as fast for the lowest silicon area.
Analog multi-stage sensing circuits have the disadvantage of having limited sensing speed capability without a significant increase in power consumption. The analog multi-stage sensing circuits are also area inefficient due to use of large “dummy” capacitors on the reference side and are not area efficient for scalable memory architectures.
Current configurations also use non-reversible reference active branches resulting in an increased area of silicon and employ an additional signal for sensing control having higher sensitivity to process variation. These configurations also have decreased noise and mismatch immunity for a given area and are not easily scalable for a desired range of memory densities.